Real Life Applications of Polyphase Filter Banks

This talk will present and revisit very briefly the concepts of Polyphase Filter Banks. The idea is to show applications with real-life and actual implementations over RFSoC devices. In this talk I want to show you what are the details to keep in mind when going from Matlab to FPGA: arthitectural decisions, clocking schemes, fixed-point issues, etc. I will make available the Vivado project together with all the source files for different RFSoC platforms.

What this presentation is about and why it matters

This talk shows how polyphase filter banks (PFBs) are used in real, high-bandwidth RF systems and how to move a working MATLAB design into FPGA hardware (specifically RFSoC). Instead of only explaining the math, the speaker walks through architectural choices you must make for an FPGA implementation: how to slice a wide spectrum into many channels efficiently, how to handle parallelized ADC outputs (the so-called gearbox / F/4 lanes), where to place mixers, and what filter designs let you reconstruct signals or build programmable filters and spectrum analyzers.

Why this matters: contemporary RF systems often sample at multi-gigasample rates and need hundreds or thousands of channelized paths (for monitoring, multi-tone generation, demodulation, or digital filtering). A naive per-channel mixer+filter approach quickly exhausts FPGA resources. PFBs give an efficient, multirate way to implement dense channelizers and synthesizers while keeping predictable performance. The talk is practical: it includes Vivado projects and working firmware for RFSoC boards, so you can reproduce and experiment on hardware.

Who will benefit the most from this presentation

• FPGA/ASIC engineers implementing RF front ends and channelizers.
• DSP engineers and students who want to take theoretical multirate concepts into hardware.
• System architects designing wideband receivers, software-defined radios, or multi-tone generators.
• Anyone using RFSoC or similar ADC/DAC-equipped SoCs who needs guidance on clocking, parallel lanes, and fixed-point trade-offs.

What you need to know

These are the core concepts and background items that will make the presentation easier to follow. If you already know these, you will be able to focus on the implementation details and trade-offs.

• Sampling and aliasing: basic discrete-time frequency domain intuition: decimation (downsampling) creates spectral replicas and requires anti-alias filters.
• Decimation / interpolation: how lowering / raising sample rate interacts with filtering and where multirate optimizations can be applied.
• Polyphase decomposition: splitting an FIR into M subfilters (polyphase components) to push decimators through the filter and reduce cost. In z-domain: \(H(z)=\sum_{r=0}^{M-1} z^{-r}E_r(z^M)\).
• DFT/FFT as a channelizer: after polyphase filtering and decimation, the final mixing across branches is an N-point DFT. Practical implementations use FFT hardware blocks: \(W_k=\sum_{l=0}^{N-1} w_l e^{-j2\pi k l/N}\).
• Analysis vs synthesis PFBs: analysis splits (channelize) the input into subbands, synthesis recombines them. Perfect reconstruction (PR) vs non-PR designs affect filter choice.
• Filter-design strategies: two practical approaches are (a) overall flat response for spectrum analyzers, and (b) QMF-style designs that produce good behavior when analysis and synthesis PFBs are cascaded (important for PR).
• Noble identity and commutator ideas: algebraic manipulations that justify moving decimators/interpolators past filters and reorganizing computation to match FPGA parallel lanes.
• RFSoC-specific blocks: these ADCs/DACs provide on-chip mixers, decimators/interpolators and parallelized outputs (gearbox/F/4). Expect to adapt the PFB to multiple parallel samples per cycle (multi-lane).
• Practical hardware concerns: clocking/synchronization, fixed-point precision and scaling, resource mapping (BRAM, DSP slices), and how to align polyphase branch indexing with FFT input lanes.

Glossary

• Polyphase filter bank (PFB): a multirate structure combining a polyphase-decomposed FIR with an FFT to create many frequency channels efficiently.
• Analysis PFB: the front-end that splits a wideband input into many lower-rate channels.
• Synthesis PFB: the inverse structure that recombines channelized signals back into a wideband stream.
• Polyphase decomposition: rewriting an FIR as M subfilters (polyphase components) so filtering and decimation/ interpolation can be reordered for efficiency.
• Noble identity: a property used to swap filtering and rate change blocks (justifies moving decimation in front of certain filter branches).
• FFT/DFT: the transform used in the PFB to implement the modulation (channel mapping) efficiently.
• Overlap structure (50% overlap): a PFB design choice where neighboring channels overlap in frequency; often corresponds to N=2 in the talk's notation.
• QMF (Quadrature Mirror Filter): a filter design approach that balances neighboring channel responses so analysis+synthesis behaves well.
• RFSoC gearbox / F/4 (multi-lane): serial-to-parallel output from on-chip converters that forces a multi-lane PFB implementation (multiple parallel samples per cycle).
• DDS (Direct Digital Synthesizer): a digital oscillator used per-channel for fine frequency tuning or multi-tone generation in the presented firmware.

A few final words

This presentation balances theory and hardware practice in a way that is rare: it explains the key algebra (polyphase decomposition, noble identities, and FFT modulation) and then demonstrates how those ideas translate into working RFSoC firmware, complete with Vivado projects and live demos (multi-tone generators, programmable filters, and a VNA-style sweep). If you want to go from MATLAB concepts to a deployable FPGA design and learn the practical pitfalls (clocking, parallel lanes, fixed-point and resource trade-offs), this talk is a great use of your time. The speaker oes an excellent job tying mathematical ideas to hands-on engineering, and you get code you can run on real hardware — a valuable combination for learning and prototyping.

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