An Introduction To High Efficiency And Multi-rate Digital Filters

There are many ways to implement digital filters and many architectures that can be chosen to achieve the optimum performance, which is typically measured in terms of MIPS and memory. This presentation will describe several optimized filtering techniques and architectures and show how they are used.

Examples will include Comb, Polyphase, Cascaded Integrator Comb (CIC) and more.

What this presentation is about and why it matters

John Edwards gives a practical introduction to high-efficiency and multi-rate digital filters: how to change sample rates (interpolation and decimation) and how to implement those operations efficiently. The talk focuses on two widely used tools in real systems: polyphase FIR filters and cascaded integrator-comb (CIC) filters, and it explains when and why each is the right choice.

This matters because changing sample rates is everywhere in DSP: audio systems that must bridge 44.1 kHz and 48 kHz domains, radio front ends that move from a high ADC rate to a narrow baseband, microphone PDM/DSD interfaces, and low-power embedded processing. Choosing the right architecture can cut MIPS, memory, and power dramatically — sometimes by orders of magnitude — and it can simplify FPGA or ASIC implementations by avoiding costly multiplies.

Who will benefit the most from this presentation

• DSP engineers designing sample-rate converters for audio, RF, or sensor interfaces.
• Embedded and FPGA/ASIC engineers who need low-cost, low-power filter implementations.
• Students and practitioners who want an implementation-oriented view of polyphase decomposition and CIC filters.
• Anyone building asynchronous sample-rate converters or multi-clock-domain systems.

What you need to know

To get the most out of the talk, you should be comfortable with these basic concepts:

• Sampling theorem and Nyquist — understand aliasing and why you must low-pass before decimation.
• FIR basics — taps, coefficients, convolution; how filter length, transition bandwidth and stop-band attenuation relate to computational cost.
• Upsampling and downsampling — the operations of inserting zeros (upsampling) and removing samples (downsampling) and why filtering is required around them.
• Polyphase idea — split a single FIR into N phase sub-filters so work is done incrementally as samples arrive. This avoids processing multiplies where the input would be zero and lets you move filtering after rate conversion (using Noble identities) to reduce cost.
• Noble identities — algebraic rules that let you commute (re-order) sampling-rate change with delays and filters to save computation. They are central to deriving efficient polyphase structures.
• CIC basics — a CIC stage combines integrator(s) (accumulate) and comb(s) (difference). CICs need no multipliers and are ideal for very large integer rate changes, but have a shallow passband and ripple. Their closed-form transfer function (for decimation/interpolation) can be written as: $H(z)=\left(\dfrac{1 - z^{-RM}}{1 - z^{-1}}\right)^N = \left(\sum_{k=0}^{RM-1} z^{-k}\right)^N$, where $N$ is stages, $R$ the rate change and $M$ the comb delay.
• Compensation (post) filters — a short FIR after a CIC sharpens the passband and achieves the required attenuation without multiplying complexity at the front end.
• Word-length growth for CIC — plan accumulator width using the rule $B \ge B_{in} + N\log_2(RM)$ to avoid overflow issues or to size packed accumulators.
• Asynchronous SRC — when clocks are not phase-locked you need a fractional-delay interpolator that tracks a tiny offset between domains; quadratic B-spline (3-tap) interpolators are a low-complexity, high-accuracy option mentioned in the talk.

Glossary

• Sample-rate conversion — changing the sampling frequency of a discrete-time signal (interpolation or decimation).
• Decimation — reducing sample rate by discarding samples after appropriate low-pass filtering.
• Interpolation — increasing sample rate by inserting samples and filtering to reconstruct the band-limited signal.
• Polyphase filter — an FIR split into phase sub-filters that operate on different sample phases to reduce redundant work.
• Commutator — the switching mechanism that distributes samples to different polyphase branches (order matters for correct response).
• CIC filter — cascaded integrator-comb filter useful for large integer rate changes; multiplier-free and efficient for hardware.
• Integrator — accumulator stage (IIR-like) in a CIC that sums samples; provides lowpass behaviour.
• Comb — differentiator-like FIR stage that subtracts delayed samples to form the overall CIC FIR response.
• Noble identities — algebraic identities that allow swapping sample-rate changes with delays/filters to produce efficient implementations.
• Fractional-delay filter — an interpolator that produces values at non-integer sample offsets (used in asynchronous SRC).

Final notes

This presentation is practical and well grounded in implementation concerns. John Edwards balances intuition (why aliasing matters, where zeros/poles sit) with engineering advice (word-length planning, when to use a post-filter, and commutation order). If you care about efficient, low-power DSP — especially on FPGAs or embedded devices — you'll come away with concrete patterns to apply immediately. Stay for the Q&A: the speaker clearly invites follow-up and offers to share code, which is a great opportunity to deepen understanding.

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