Fixed Point Math in the Open Logic FPGA Standard Library

FPGAs excel at high-performance DSP applications due to their parallel processing capabilities, but fixed-point algorithm implementation often suffers from fragmented toolchains. DSP algorithms are typically developed in Python for rapid prototyping, but translating these models to HDL requires manual recoding with inconsistent fixed-point support across Python and VHDL/Verilog. This leads to lengthy verification cycles and potential bit-exactness errors. Additionally, the absence of standardized libraries forces developers to repeatedly implement basic elements like FIFOs, CDCs, and delay lines.

Open Logic, a vendor-independent standard library, addresses both of these challenges. Its fixed-point mathematics framework provides a unified notation that remains consistent across Python and HDL implementations in both VHDL and Verilog. This common syntax enables straightforward manual translation with minimal transcription errors, while automated verification tools confirm bit-exact equivalence between Python prototypes and HDL implementations. This approach also allows for parametrizable, reusable HDL code with automatic word-width scaling.

This talk will briefly cover Open Logic's core concepts, including its library of standard components (FIFOs, CDCs, and delay lines). We will then demonstrate a complete fixed-point development workflow using a practical example. Attendees will see the process from initial Python model definition through HDL implementation to bit-exact verification, highlighting the time savings and reduced error potential compared to traditional manual approaches.

Before you watch: Fixed-point math and the Open Logic FPGA library — a practical primer

This short talk addresses a very practical, recurring problem for engineers who build DSP systems on FPGAs: how to move a numerically sensitive algorithm from a fast prototype (Python/NumPy) into high-performance, bit-exact hardware without re-inventing the plumbing every time. If you design controllers, filters, NCOs, or any streaming DSP on FPGAs, this presentation will show a workflow and tooling that reduce translation errors, speed verification, and produce reusable hardware building blocks.

Why this matters in practice

FPGA projects often slow down around two tasks: (1) choosing fixed-point formats and getting quantization right, and (2) re-implementing basic infrastructure (FIFOs, CDCs, delay lines, register stages) that should be solved once and reused. Mistakes here cause subtle functional errors, long verification cycles, and missed performance targets. Open Logic aims to be a vendor-independent standard library that bridges the gap between Python prototypes and HDL implementations, with a focus on fixed-point math, clear conventions, and tools for bit-exact co-simulation.

Key concepts to know before you dive into the talk

• Binary fixed-point format: A fixed-point number is described by a sign bit (optional), integer bits, and fractional bits. The fractional resolution is 2^-F (you can read it as \\(2^{-F}\\) if you use math), and the integer bits set the nominal range (about \\(2^{I}\\)). Understanding how many bits you need for dynamic range and how many for precision is the core of fixed-point design.
• Quantization, rounding and saturation: When operations grow bit widths (for example multiplication), you must choose how to reduce back to the target format: truncate, round-to-nearest, or saturate on overflow. These choices affect steady-state error, transient behavior, and worst-case clipping.
• Pipeline stages and latency: High-performance FPGA code uses pipelining—breaking computations across registers—to reach higher clock speeds. That changes timing and requires you to balance registers across parallel paths so valid signals align. Open Logic components expose pipelining and register-count options so you can trade latency for throughput predictably.
• Handshaking and valid signals: Streaming components typically use a valid/data handshake. Know how a valid pulse travels through pipelines and how misaligned latencies create spikes or gated values; the library handles much of this if you use its entities.
• Co-simulation and bit-exact verification: The talk demonstrates writing stimulus and expected outputs from Python into hex files and injecting them into HDL testbenches. This lets you check that Python fixed-point behavior and the synthesized HDL are identical bit-for-bit for the same input vectors.
• Two complementary approaches in the library: NCL-Fix (function-oriented) is compact for low-level ops; Open Logic Fix (entity/component-oriented) wraps operations into pipeline-aware building blocks for high performance and easier wiring. You’ll see both approaches.

What background will help you get the most out of the presentation

• Familiarity with binary numbers and the idea of fixed-point vs floating-point.
• Basic experience with an HDL (VHDL or Verilog) and with Python scripting (NumPy is useful but not mandatory).
• Some understanding of DSP blocks like a PI controller or filter—enough to follow a block diagram and identify nodes where quantization matters.

Don’t worry if you are not an HDL master: the talk is practical and shows a one-to-one mapping from Python models to HDL entities. You’ll see the same numeric formats used in both languages, plus simulation utilities that verify bit-exact behavior.

What to expect — high level (no spoilers)

• A quick tour of Open Logic’s philosophy and organization (why a standard FPGA library matters).
• A focused demo of fixed-point workflow: write a Python floating-point model, convert to fixed-point, run a fixed-point Python simulation, and then translate to HDL—then run co-simulation to confirm bit-exactness.
• Illustrations of practical issues: format selection, rounding/saturation, pipelining choices, and how the library’s entities make these explicit and configurable.
• A look at both VHDL and Verilog integration, and how the library helps with common blocks like FIFOs and CDCs beyond arithmetic.

Why invest your time now? If you work with DSP on FPGAs, you likely repeat the same fixed-point and infrastructure work on every project. This talk gives concrete methods and open-source components that reduce that repetition, tighten verification, and help you reach higher clock speeds without hand-tuning every register. Watching will give you a practical toolset to prototype faster in Python and move to reliable HDL with confidence.

Ready to watch? Bring curiosity about numerical choices and an appetite for practical engineering shortcuts—this talk is about saving you time and preventing the small, costly bugs that hide in fixed-point transitions.

This overview is AI-generated from the session transcript. Spot an issue? Let us know.