FPGA are devices where DSP algorithms fit perfectly. The MACC blocks in FPGA are almost designed for this kind of algorithms but they are also a limited resource. Small FPGA like Spartan 7 or Intel MAX10 have a reduced number of MACC blocks but well used, that little amount can be enough to implement even high-order filters. This session talks about how to optimize the number of MACC blocks used in DSP algorithms by applying technics like folding, optimizing the number of bits, or changing the structure of the DSP algorithm. During the session, we will see the implementation results of the different technics and how much we can reduce the amount of MACC blocks and also the number of general resources used.