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Signal Processing with FPGA, Python & no RTL Design!

Adam Taylor- Watch Now - Duration: 01:41:52

To take full advantage of this workshop, you'll need an Arty Z7 board.  If you decide to purchase one, make sure to: 

  1. Select the Z7-20 version.
  2. Enter the promo code DSPARTYZ725 to save 25%

Before attending the workshop, make sure to download and install:

  1. Pynq 2.6 for the PYNQ Z1 http://bit.ly/pynqz1_v2_6
  2. Vitis 2020.1 this includes Vivado and Vitis HLS - https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis/archive-vitis.html
  3. Check out this github link for more workshop material, including a pdf of the slides: https://github.com/AdiuvoEngineering/EOC_DSP

Developing programmable logic solutions is moving up the levels of abstraction.

In this session we will use the Arty Z7 board and the Xilinx PYNQ framework to accelerate signal processing algorithms (FFT, FIR Filters) in programmable logic using with a combination of Python and High-Level Synthesis (C/C++). Techniques such as this will allow us to leverage the processing capabilities of programmable logic without the requirement to develop solutions using traditional FPGA Register Transfer Languages. This enables smaller, more power-efficient solutions.

This session will introduce the PYNQ framework and explain how it interacts with the programmable logic. We will then explore how we can use HLS – what is it, how do we go from untimed C to logic gates and what optimisations do we need. Finally, we will look at how we can build PYNQ overlays using IP Integrator which can be loaded onto the Arty Z7 for use with our Python application using Jupyter Notebooks / Labs. 

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Score: 0 | 2 months ago | 1 reply

Hi Adam,
Really great presentation. Unfortunately I had to see after work and missed the information regarding the material (links for the project etc.) you used in this presentation. I did get the slide because they show on your page.

Score: 0 | 2 months ago | 1 reply

Click on the 'Description' tab (right at the top here, under the large image) and everything should be there.

Score: 0 | 2 months ago | no reply

Thank you

09:02:35	 From  Robert Edwards : will this session be recorded for later playback (can't pay full attention right now)
09:02:57	 From  Robert Edwards : thanks
09:03:23	 From  Leonard : yeah 5 am here
09:30:33	 From  Leonard   to   Stephane Boucher(Direct Message) : for this workshop I thought there was a download list to use on your computer. Did that go away? I cant seem to find it
09:31:01	 From  Stephane Boucher   to   Leonard(Direct Message) : https://www.dsponlineconference.com/workshop/Signal_Processing_with_FPGA_Python_and_no_RTL_Design
09:31:10	 From  Stephane Boucher   to   Leonard(Direct Message) : Click on 'Description'
09:34:53	 From  Leonard   to   Stephane Boucher(Direct Message) : ok that was the issue I was in in Q&A
09:36:07	 From  mnapier : What version of Vivado are you using?
09:36:13	 From  Adiuvo Engineering : 2020.1
09:36:31	 From  mwf : Adam, what components are on the SDCard image?
09:37:13	 From  Leonard : 2019.1 ??
09:37:47	 From  mnapier : I have a PYNQ-Z2 board.  I see 2.5 for it.  What version of Vivado for it?
09:40:35	 From  Pablo : any difference between using Pynq on this board or on a new Kria?
09:45:31	 From  mwf : Can you see any of the source for the IP, e.g. package def or whatever?
09:47:03	 From  wessel lubberhuizen : When synthesizing, is there any resource sharing possible between IP blocks? Like if you have a design that runs at a low clock speed, can you share DSP slices between an FFT and a Filter?
09:47:42	 From  Robert Edwards : can you modify the code in any of the selected IP blocks?
09:53:15	 From  Henk : did you disable sgdma due to the nature of the streaming data?
09:53:54	 From  Leonard : Is the pynq dma aware? or does the user need to do scatter gather lists?
09:58:50	 From  Henk : Hi Adam, what was the HP DMA width here? 128 bits?
09:59:47	 From  Henk : how to combine it if you need higher bandwidth?
10:05:37	 From  Pablo : the default pynq images (pynq.io) already have a default bitstream/ design?
10:07:23	 From  Adiuvo Engineering : https://github.com/AdiuvoEngineering/EOC_DSP
10:10:32	 From  Henk : Adam, if i wnat to rebuld this all with a ZCU106.. is there a link which describes the tasks for manually building the images
10:10:55	 From  Adiuvo Engineering : www.adiuvoengineering.com
10:11:28	 From  mwf : For those new to PYNQ and Vivado, can you recommend an on-boarding process to ramp-up quickly?
10:11:42	 From  Henk : ok you naem petalinux but.. I am a yocot guy.. I assume I can do it without the petalinux tool?
10:13:20	 From  mwf : Thank you @Marcin!
10:13:46	 From  Dave Comer : This process (IE The Vivado design) should work for the Ulthra96-v2?
10:14:24	 From  Marcin Puchlik : Are you running http server on your Zynq board?
10:15:52	 From  Marcin Puchlik : so your board is in the same local network as your computer? I assume you are connected to the board using not only USB but also Ethernet cable?
10:16:10	 From  Pablo : Have you tried DFX design with PYNQ? It works well?
10:16:53	 From  Dave Comer : Did that last night (Ultra) worked great!
10:17:03	 From  Dave Comer : Yes
10:21:26	 From  Marcin Puchlik : Can we install any 3rd party library using e.g. pip on the board? is there any difference between this Jupyter notebook and 'normal' one running lets say from conda environment?
10:24:21	 From  Leonard   to   Stephane Boucher(Direct Message) : this recording is going to be available later?
10:25:26	 From  Pablo : all xilinx IPs have their library in pynq?
10:28:17	 From  Stephane Boucher   to   Leonard(Direct Message) : Yes
10:30:51	 From  Henk : how do you decide if this rate is not limited by the memory interface bandwidth on the PS HP port?
10:33:12	 From  Leonard   to   Stephane Boucher(Direct Message) : where on your web site do you suggest us going?
10:33:14	 From  Dave Comer : Can we email you directly with questions?
10:33:16	 From  Leonard   to   Stephane Boucher(Direct Message) : for this demo
10:33:24	 From  Henk : it is a very nice presentation Adam
10:33:35	 From  Adiuvo Engineering : adam@adiuvoengineering.com
10:33:40	 From  mwf : This was excellent, Adam.  Gotta get back to work!
10:33:42	 From  Dave Comer : I should have said "May"
10:33:52	 From  Leonard : where on the your web site do you suggest us going
10:33:57	 From  Leonard : for this demo
10:33:59	 From  Pablo : Nice Work Adam
10:34:00	 From  mnapier : So can I put in a register interface and get to it w/o having to do a device driver?
10:34:16	 From  Adiuvo Engineering : https://github.com/AdiuvoEngineering/EOC_DSP
10:34:27	 From  Dave Comer : Thanks for this and all of your past contributions. Been following you since 2011...
10:37:20	 From  wessel lubberhuizen : can you do partial reconfiguration of the fpga in pync?
10:38:12	 From  Rob K. : Great presentation. Thanks for putting this together!
10:38:44	 From  mnapier : Hard to do a PYNQ system for say a ZedBoard?
10:39:20	 From  Pablo : I have seen some code generating an ILA chipscope from Pynq.. do you know any special technique to debug from pynq?
10:39:23	 From  Dave Comer : This may be a bit off-topic, but, are you aware of any low-cost (<$1k) RFSoC dev boards or aware if any are coming?
10:40:44	 From  Dave Comer : The PYNQ demo on the RFSoC was killer.
10:41:39	 From  Dave Comer : I think that one is academic priced.... :(
10:41:53	 From  Dave Comer : :)
10:42:02	 From  Dave Comer : Digilent ?
10:42:12	 From  wessel lubberhuizen : is there something like pyaltera?
10:42:33	 From  Pablo : Versal better ;)
10:43:31	 From  Henk : Tnx Adam! Again.
10:43:49	 From  Dave Comer : You da man with da plan!
10:44:05	 From  mwf : Thank you, all.  This was a great jump start!
10:44:27	 From  wessel lubberhuizen : thnx!
10:44:34	 From  Pablo : thanx