Signal Processing with FPGA, Python & no RTL Design!Status: Available Now
To take full advantage of this workshop, you'll need an Arty Z7 board. If you decide to purchase one, make sure to:
- Select the Z7-20 version.
- Enter the promo code DSPARTYZ725 to save 25%
Before attending the workshop, make sure to download and install:
- Pynq 2.6 for the PYNQ Z1 http://bit.ly/pynqz1_v2_6
- Vitis 2020.1 this includes Vivado and Vitis HLS - https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis/archive-vitis.html
- Check out this github link for more workshop material, including a pdf of the slides: https://github.com/AdiuvoEngineering/EOC_DSP
Developing programmable logic solutions is moving up the levels of abstraction.
In this session we will use the Arty Z7 board and the Xilinx PYNQ framework to accelerate signal processing algorithms (FFT, FIR Filters) in programmable logic using with a combination of Python and High-Level Synthesis (C/C++). Techniques such as this will allow us to leverage the processing capabilities of programmable logic without the requirement to develop solutions using traditional FPGA Register Transfer Languages. This enables smaller, more power-efficient solutions.
This session will introduce the PYNQ framework and explain how it interacts with the programmable logic. We will then explore how we can use HLS – what is it, how do we go from untimed C to logic gates and what optimisations do we need. Finally, we will look at how we can build PYNQ overlays using IP Integrator which can be loaded onto the Arty Z7 for use with our Python application using Jupyter Notebooks / Labs.